Stacked chip package

专利摘要:
PURPOSE: A stacked chip package is provided to make it possible to package in narrow bonding space and decrease the number of bad chips by determining whether a chip is good or not before a packaging process. CONSTITUTION: A semiconductor chip with many electric contact holes is prepared and burn-in-tested to be determined whether it is good or not. Good chips passing the test are attached on a PCB(220) with glue(224). A conductive pattern(226) on the PCB is connected to a chip pads on the holes(20) with bonding wires(240). The semiconductor chip and bonding wires are covered with epoxy(250). Solder balls(222) are attached on the ball lands(260).
公开号:KR20030029680A
申请号:KR1020010061422
申请日:2001-10-05
公开日:2003-04-16
发明作者:박상욱
申请人:주식회사 하이닉스반도체；
IPC主号:

专利说明:

Stacked chip package
[18] The present invention relates to a method, and more particularly, to a laminated chip package having a structure in which a plurality of semiconductor chips are stacked and a manufacturing method thereof.
[19] With the trend toward thinner and shorter electronic devices, high-density and high-mounted packages are becoming an important factor.In the case of computers, a large amount of random access memory (RAM) and fresh memory as the storage capacity increases. Like the Flash Memory, the size of the chip grows naturally, but the package is being studied to be smaller in accordance with the above requirements.
[20] Here, various methods that have been proposed to reduce the size of a package include, for example, a multi chip package (MCP) and a multi chip module (MCM) in which a plurality of chips or packages are mounted. In particular, there are limitations in manufacturing the semiconductor chip and the package because they are mounted in a planar arrangement method on the substrate.
[21] In order to overcome this limitation, a package technology in which a plurality of chips having the same storage capacity are integrally stacked has been proposed, which is commonly referred to as a stacked chip package.
[22] At present, the above-described stacked chip package technology can reduce the manufacturing cost of the stacked chip package in a simplified process, and also has advantages such as mass production. There is a shortcoming.
[23] 1 is a cross-sectional view of a stacked chip package according to the prior art.
[24] As shown in FIG. 1, the stacked chip package 100 according to the related art has a structure in which a plurality of semiconductor chips 120, 130, and 140 are mounted in a planar manner using a substrate 110.
[25] Each of the semiconductor chips 12, 130, and 140 is attached to the mounting area of the upper surface of the substrate 110 by an adhesive 114, and a plurality of bonding pads 122, 132, and 142 are provided on the surface opposite to the surface attached to the substrate 110. ) Has a formed structure.
[26] The bonding pads 12, 22, and 32 correspond to the conductive patterns 112 formed on the upper surface of the substrate 110, and are electrically connected to each other by the bonding wires 124, 134, and 144.
[27] In addition, the package body 150 is formed by encapsulating an epoxy-based encapsulating resin in order to protect the electrical connection portions formed on the semiconductor chips 120, 130, 140 and the upper surface of the substrate 110.
[28] The conductive pattern 112 of the substrate 110 is a wiring layer for electrically connecting the semiconductor chips 120, 130, and 140 to the solder balls 160.
[29] The semiconductor chips 120, 130, and 140 are electrically connected to each other by a circuit pattern formed on the upper surface of the substrate 110, or the bonding pads 12, 22, and 32 of the semiconductor chip are simultaneously connected to the bonding wires 124, 134, and 144 on the conductive pattern 112. It may be electrically connected by bonding.
[30] Conventionally, a packaging process is performed after a test operation such as a proving process is performed on each semiconductor chip. However, the defective chips generated during the packaging process and subsequent burn-in tests cannot be found in advance, and the loss of the products due to these defective chips was large.
[31] In addition, there is a problem in that a bonding space takes up a lot by using a bonding wire.
[32] Accordingly, the present invention has been made to solve the above-mentioned problems, and can be packaged even in a narrow bonding space, and the stacked chip package which can reduce the loss due to the bad chip by performing the bad chip discrimination before the packaging process proceeds. Its purpose is to provide a method for its manufacture.
[1] 1 is a cross-sectional view of a laminated chip package according to the prior art.
[2] 2 is a plan view of a stacked chip package according to a first embodiment of the present invention.
[3] 3 is a perspective view showing a part of a stacked chip package according to a first embodiment of the present invention.
[4] 4 is a cross-sectional view of a stacked chip package according to a first embodiment of the present invention.
[5] 5A through 5F are cross-sectional views illustrating a process of manufacturing a stacked chip package according to a first embodiment of the present invention.
[6] 6 is a cross-sectional view of a stacked chip package according to a second embodiment of the present invention.
[7] 7 is a cross-sectional view of a stacked chip package according to a third embodiment of the present invention.
[8] 8 is a cross-sectional view of a stacked chip package according to a fourth embodiment of the present invention.
[9] 9A to 9B are partially enlarged views of a stacked chip package according to a fourth exemplary embodiment of the present invention.
[10] 10 is a cross-sectional view of a stacked chip package according to a fifth embodiment of the present invention.
[11] 11 is a cross-sectional view of a stacked chip package according to a sixth embodiment of the present invention.
[12] 12 is a cross-sectional view of a stacked chip package according to a seventh embodiment of the present invention.
[13] Explanation of symbols for main parts of the drawings
[14] 20, 21, 22, 23. Grooves 210, 212, 214, 216. Semiconductor chips
[15] 222. Borland 224. Adhesives
[16] 240. Bonding Wire 226. Conductive Pattern
[17] 250. Molded article 260. Solder ball
[33] The laminated chip package of the present invention for achieving the above object is a semiconductor chip having a laminated structure, a recess groove formed on one side or the other side of the semiconductor chip, the metal wiring is connected to the chip pad is arranged, the semiconductor chip on the upper surface A printed circuit board to which the printed circuit board is attached, a first conductive pattern attached to the bottom surface of the printed circuit board, a second conductive pattern connecting the metal wiring of the recessed groove and the printed circuit board, and a semiconductor chip and the second conductive pattern Characterized by including.
[34] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[35] 2 is a plan view of a multilayer chip package according to a first embodiment of the present invention, and FIG. 3 is a perspective view showing a part of the multilayer chip package according to the first embodiment of the present invention.
[36] 4 is a cross-sectional view taken along the line II of FIG. 2.
[37] As shown in FIGS. 2 and 3, the stacked chip package of the present invention includes a first semiconductor chip 210 having a plurality of first recessed grooves 20 formed at one side thereof and a plurality of second recessed grooves 21 at the other side thereof. ) Is formed of a second semiconductor chip 212 is arranged in a row, the third semiconductor chip 214 having a plurality of third recessed grooves 22 formed on one side, the fourth recessed grooves 23 formed on the other side Four semiconductor chips 216 are arranged in rows with respect to the first semiconductor chip 210 and the second semiconductor chip 212. A plurality of chip pads (not shown) are formed in the concave groove 20.
[38] As shown in FIGS. 2 and 4, the printed circuit board 220 includes the first, second, third and fourth semiconductor chips 210 each having an adhesive 224 thereon. 212, 214, and 216 are attached, and a plurality of solder balls 260 are attached to the ball land 222 on the bottom surface. In addition, a conductive pattern 226 is formed on one side of the upper surface of the printed circuit board 220.
[39] The conductive pattern 226 is electrically connected to the chip pads of the first, second, third and fourth recessed grooves 20, 21, 22, and 23 of the semiconductor chip by respective bonding wires 240. do.
[40] The semiconductor chips 210, 212, 214, and 216 and the bonding wire 240 are covered with a molding 250.
[41] 5A through 5F are cross-sectional views illustrating a process of manufacturing a stacked chip package according to a first exemplary embodiment of the present invention. FIGS. 5A through 5C illustrate only process cross-sectional views of fourth semiconductor chips of semiconductor chips for convenience.
[42] In the method of manufacturing a multilayer chip package according to the first embodiment of the present invention having the above structure, as shown in FIG. 5A, first, a first insulating layer 14 is deposited on the entire surface of the substrate 10, and the first insulating layer is formed. The 14 is etched to form the openings 15 exposing the chip pads 12.
[43] Subsequently, as illustrated in FIG. 5B, after depositing a metal layer on the first insulating layer 14 by a sputtering method, the metal layer is etched to form a metal wiring 16 covering the opening 15. At this time, the metal wiring 16 has a compound or a composite multilayer structure with copper, nickel, copper and nickel.
[44] Subsequently, as shown in FIG. 5C, a second insulating film 18 having a thickness of 5 μm is deposited on the resultant substrate using an epoxy resin or a polyimide resin, and then a part of the second insulating film is deposited. The etching process forms the recessed grooves 23 to complete the semiconductor chip manufacturing process as shown in FIG. 3.
[45] Thereafter, as shown in FIG. 5D, the resultant semiconductor chip is mounted in the test socket 270, and then burn in test is performed to check whether the defective chip is present.
[46] The test socket 270 has a plurality of signal probe pins 274 formed on a bottom surface thereof, and a plurality of contact pins 216 connected to metal wires on respective recessed grooves on an inner surface of an inner space into which a semiconductor chip is inserted. Formed.
[47] The contact pin 216 has an elastic ring or spring shape, and has a structure capable of electrical contact with the metal wiring by a mechanical elastic force.
[48] Subsequently, as illustrated in FIG. 5E, the high quality semiconductor chips 214 and 216 selected through the test are attached to the printed circuit board 220 by the adhesive 224.
[49] Next, the conductive pattern 226 of the printed circuit board 220 and the metal wirings on the respective recessed grooves 22 and 23 are bonded by the bonding wire 240.
[50] Thereafter, as illustrated in FIG. 5F, a molding member 250 covering the semiconductor chips 214 and 216 and the bonding wire 240 is formed using a molding material such as an epoxy resin.
[51] Subsequently, the solder balls 260 are attached to the bonding pads 222 of the printed circuit board 220 to complete the manufacturing of the contact chip package.
[52] 6 is a cross-sectional view of a stacked chip package according to a second embodiment of the present invention.
[53] In the second embodiment of the present invention, as shown in FIG. 6, the packaging process is performed in the same manner as the first embodiment of the present invention, but instead of the solder ball of the first embodiment of the present invention, the conductive pin 282 is used. use.
[54] 7 is a cross-sectional view of a stacked chip package according to a third embodiment of the present invention.
[55] In the third embodiment of the present invention, as shown in FIG. 7, the manufacturing process of the stacked chip package is performed by using the contact pins 292 instead of the bonding wires in the first and second embodiments of the present invention. In this case, the contact pins 292 are electrically connected to the metal wires on the recesses 22 and 23 of the semiconductor chips 214 and 216.
[56] In addition, the substrate 290 may be used as a test socket, and a conductive pin 298 is formed under the substrate.
[57] 8 is a cross-sectional view of a stacked chip package according to a fourth embodiment of the present invention.
[58] In the fourth embodiment of the present invention, as shown in Figure 8, the package manufacturing process proceeds in the same manner as the third embodiment of the present invention, the solder ball 306 instead of the connecting pin of the third embodiment of the present invention This is used.
[59] The connection pin 302 includes a conductive pin 302b and a plating layer 302a plated on the conductive pin 302b. In this case, a solder is used as the plating layer 302a.
[60] 9A to 9B are partially enlarged views of a stacked chip package according to a fourth exemplary embodiment of the present invention.
[61] Referring to the process of attaching the connecting pin 302 to the metal wiring, first contacting the configured connecting pin 302 and the metal wiring 22 of the semiconductor chip 214, as shown in Figure 9a, infrared By performing a reflow process using a lamp (not shown) or the like, as shown in FIG. 9B, the plating layer 302b is melted and the connecting pin 302 is joined to the metal wiring of the recessed groove.
[62] 10 is a cross-sectional view of a stacked chip package according to a fifth embodiment of the present invention.
[63] In the semiconductor chip of the fifth embodiment of the present invention, as shown in FIG. 10, a first semiconductor chip 410 having a plurality of first recessed grooves 40 formed on one side and a plurality of second recessed grooves 41 on the other side thereof. ) Is formed of a second semiconductor chip 412 is arranged in a row, a third semiconductor chip 414 having a plurality of third recessed grooves 42 formed on one side and a plurality of fourth recessed grooves 43 formed on the other side. Four semiconductor chips 416 are stacked on the first semiconductor chip 410 and the second semiconductor chip 412, respectively.
[64] That is, the first recessed grooves 40 of the first semiconductor chip 410 and the third recessed grooves 42 of the third semiconductor chip 414 correspond to each other, and the second recessed grooves of the second semiconductor chip 412 correspond to each other. The 41 and the fourth recessed grooves 43 of the fourth semiconductor chip 416 are respectively in corresponding positions.
[65] The first semiconductor chip 410 and the second semiconductor chip 412 are attached to the printed circuit board 420 by an adhesive 424 on the upper surface, and the first semiconductor chip 410 and the first semiconductor chip 410 are attached to the printed circuit board 420 by an adhesive 424. The third semiconductor chip 414 is attached, and the second semiconductor chip 214 and the fourth semiconductor chip 416 are attached.
[66] The semiconductor chips 410, 412, 414, and 416 according to the fifth embodiment of the present invention configured as described above are electrically conductive patterns 426 on the substrate 420 by the bonding wires 430 and the conductive material layer 440. Connected with In this case, a solder ball 460 is attached to the bonding pad 422 on the lower surface of the substrate 420.
[67] The semiconductor chips 410, 412, 414, and 416 and the bonding wire 430 are covered with a molding member 450.
[68] 11 is a cross-sectional view of a stacked chip package according to a sixth embodiment of the present invention.
[69] In the sixth embodiment of the present invention, as shown in FIG. 11, the shape of the molding body is modified in the fifth embodiment.
[70] The molding body 550 according to the embodiment of the present invention covers the first, second, third, and fourth semiconductor chips 510, 512, 514, 516, and the bonding wire 530, and the third semiconductor. One surface of the chip 514 and the fourth semiconductor chip 516 may be exposed. A heat sink (not shown) is mounted on the exposed portion of the semiconductor chip.
[71] 12 is a cross-sectional view of a stacked chip package according to a seventh embodiment of the present invention.
[72] In the seventh embodiment of the present invention, as shown in Fig. 12, the shape of the semiconductor chips stacked in the fifth embodiment is modified.
[73] In the semiconductor chip according to the seventh exemplary embodiment of the present invention, as shown in FIG. 12, a first semiconductor chip 610 having a plurality of first recessed grooves 60 formed on one side thereof and a plurality of second recessed grooves on the other side thereof is shown. The second semiconductor chip 612 having the 61 is arranged in a row, and the third semiconductor chip 614 is formed on one side and the third semiconductor chip 614 is smaller than the size of the first semiconductor chip and the other on the other side. The fourth recessed groove 63 is formed and the fourth semiconductor chip 616, which is smaller than the size of the second semiconductor chip, is stacked on the first semiconductor chip 610 and the second semiconductor chip 612, respectively. Side surfaces of the first semiconductor chip and the third semiconductor chip and side surfaces of the second semiconductor chip and the fourth semiconductor chip form a step shape.
[74] In addition, the metal wiring of the first semiconductor chip 610 and the conductive pattern 626 are connected by the first bonding wire 670, and the metal wiring of the second semiconductor chip 612 is connected by the second bonding wire 672. And the conductive pattern 626 are connected.
[75] In addition, the metal wiring of the third semiconductor chip 614 and the metal wiring of the first semiconductor chip 610 are connected by the third bonding wire 674, and the fourth semiconductor chip 676 is connected by the fourth bonding wire 676. The metal wire of 616 and the metal wire of the second semiconductor chip 612 are connected.
[76] As described above, in the present invention, the integration degree of the semiconductor chip can be improved through the stacked structure of the semiconductor chip.
[77] In addition, in the present invention, since the packaging process is performed after the determination of the defective chip, loss of the product due to the defective chip can be prevented.
[78] In addition, bonding is possible in a narrow space by using the recess of the semiconductor chip.
[79] In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

权利要求:
Claims (8)
[1" claim-type="Currently amended] A semiconductor chip having a laminated structure,
A recess groove formed on one side or the other side of the semiconductor chip and having metal wirings connected to the chip pads;
A printed circuit board having the semiconductor chip attached thereto;
A first conductive pattern attached to the bottom surface of the printed circuit board;
A second conductive pattern connecting the metal wiring of the recess and the printed circuit board;
And a molding body covering the semiconductor chip and the second conductive pattern.
[2" claim-type="Currently amended] The multilayer chip package of claim 1, wherein the first conductive pattern is a solder ball.
[3" claim-type="Currently amended] The multilayer chip package of claim 1, wherein the first conductive pattern is a conductive pin.
[4" claim-type="Currently amended] The multilayer chip package of claim 1, wherein the second conductive pattern is a bonding wire.
[5" claim-type="Currently amended] The multilayer chip package of claim 1, wherein the second conductive pattern is a contact pin.
[6" claim-type="Currently amended] The multilayer chip package of claim 1, wherein an adhesive interposed between the substrate and the semiconductor chip is added.
[7" claim-type="Currently amended] The method of claim 1, wherein the semiconductor chip,
A first semiconductor chip having respective first recessed grooves in which a first metal wiring connected to the first chip pad is arranged on one side;
A second semiconductor chip having a second recessed groove in which a second metal wiring connected to the second chip pad is arranged on the other side;
Third recessed grooves each having a third metal wiring connected to the third chip pad are arranged on one side thereof, and the third recessed grooves are stacked on the first semiconductor chip so that the third recessed grooves and the first recessed grooves correspond to each other. 2 semiconductor chip,
Fourth recessed grooves each having a fourth metal wiring connected to a third chip pad arranged on the other side are formed, and the fourth stacked grooves are stacked on the second semiconductor chip so that the fourth recessed grooves and the second recessed grooves correspond to each other. A laminated chip package comprising four semiconductor chips.
[8" claim-type="Currently amended] The method of claim 1, wherein the semiconductor chip
A first semiconductor chip having respective first recessed grooves in which a first metal wiring connected to the first chip pad is arranged at one side;
A second semiconductor chip having a second recessed groove in which a second metal wiring connected to the second chip pad is arranged on the other side;
A third semiconductor chip having a third metal groove arranged on one side thereof and having a third metal wiring connected thereto, the third semiconductor chip being stacked on the first semiconductor chip and exposing the first recess groove;
Fourth recessed grooves each having a second metal interconnection connected to a fourth chip pad formed on the other side are formed, and are formed of a fourth semiconductor chip stacked on the second semiconductor chip to expose the second recessed grooves. Stacked chip package characterized by.

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同族专利:

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公开号 | 公开日

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KR100470387B1|2005-02-07|

引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
2001-10-05|Application filed by 주식회사 하이닉스반도체

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2001-10-05|Priority to KR10-2001-0061422A

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2003-04-16|Publication of KR20030029680A

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2005-02-07|Application granted

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2005-02-07|Publication of KR100470387B1

优先权:

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申请号 | 申请日 | 专利标题

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KR10-2001-0061422A|KR100470387B1|2001-10-05|2001-10-05|stacked chip package|